SPECIAL SEMICONDUCTOR DEVICES
This article describes several special semiconductor devices, such as silicon controlled rectifiers, triacs, diacs, unijunction transistors, and field effect transistors. Also described are integrated circuits and the use of operational amplifiers.
Figure 1: Silicon Controlled Rectifier (SCR)Although it is not the same as either a diode or a transistor, the SCR combines features of both. Circuits using transistors, or rectifier diodes, may be greatly improved through the use of SCRs.
The basic purpose of an SCR is to function as a switch that can turn on or off large amounts of power. It performs this function with no moving parts that wear out and no points that require replacing. There can be a tremendous power gain in the SCR; in some units, a very small triggering current is able to switch several hundred amperes without exceeding its rated abilities. The SCR can often replace much slower and larger mechanical switches.
The SCR is an extremely fast switch. It is difficult to cycle a mechanical switch several hundred times a minute, yet SCRs can be switched 25,000 times a second. It takes just microseconds (millionths of a second) to turn SCRs on or off. Varying the time that a switch is on, as compared to the time that it is off, regulates the amount of power flowing through the switch. Since most devices can operate on pulses of power (alternating current is a special form of alternating positive and negative pulses), the SCR can be used readily in control applications. Motor speed controllers, inverters, remote switching units, controlled rectifiers, circuit overload protectors, latching relays, and computer logic circuits all use the SCR.
Figure 2: SCR Construction and Schematic Diagram
Figure 3: The SCR and Its Equivalent CircuitsThe equivalent circuit will be biased just like the actual SCR shown in Figure 3. First, the anode of the circuit will be made positive with respect to the cathode, but the gate will be left open. Under these conditions, the NPN transistor will not conduct because its emitter junction will not be subjected to a forward bias voltage, which can produce a base current. This will cause the PNP transistor to turn off because the NPN transistor will not be conducting and, therefore, will not allow a base current to flow through the emitter junction of the PNP transistor.
The equivalent SCR circuit will not allow current to flow from its cathode to its anode under these conditions.
This first state is called the forward blocking region. The SCR does not conduct from anode-to-cathode.
In its second operating state, the SCR is switched to its high conduction region. This will occur if the cathode-anode voltage is increased. At some point, the SCR begins full conduction. This point is called the forward breakover voltage (VBO), as shown in Figure 4.
Figure 4: SCR Characteristic CurveAt the forward breakover voltage, the current carriers acquire sufficient energy and speed to produce an avalanche effect, increasing the amount of current flow and decreasing the anode to cathode opposition. When the opposition of Q1 in the equivalent circuit decreases, the forward bias on Q2 increases. This will cause cathode to anode current flow through the SCR to increase. This can be seen by examining the characteristic curve in Figure 5.
Figure 5: Decreased Forward Breakover Voltage (VBO)Note that very little current will flow from anode to cathode until the anode to cathode voltage is equal to the forward breakover voltage (VBO). After VBO, the SCR is switched from an "off" state of high anode to cathode resistance to an "on" state of low anode to cathode resistance with high forward current. It should also be noted that the anode to cathode voltage would decrease to a value that is much lower than VBO.This is important because it indicates that the SCR will continue to conduct a flow of forward current after it has been switched to its "on" state even if the supply voltage is decreased below its forward breakover voltage. In other words, if the supply voltage is increased to VBO, the SCR will be switched from the "off" state to the "on" state. When the SCR is in its "on" state, a flow of forward current will flow even when the supply voltage is decreased below VBO.
Forward current will continue until the supply voltage is reduced to a point that produces a value of forward current that is less than the SCRs holding current. Holding current is the minimum value of anode current that will allow the SCR to remain in its turned "on" state. The SCR cannot be switched off until its anode current is decreased below its holding current.
In examining the curve, it should be noted that the SCR functions like a conventional diode when a reverse voltage is applied to it (negative at the anode with reference to the cathode). Very little reverse current flows until a critical value of reverse voltage is applied. When the reverse voltage is increased beyond this point, the SCR breaks down and reverse avalanche current will flow. This point is called the reverse breakdown voltage.
Now, let us consider the effects of a positive potential at the gate with reference to the cathode. A positive potential at the gate will forward bias the gate cathode circuit. This will produce a flow of current between the cathode and the gate, which will increase the number of available current carriers and lower the anode to cathode opposition of the SCR. As a result, the value of anode to cathode voltage that is necessary to produce breakover is reduced.
The SCR will be switched to a high state of conduction at a lower anode to cathode voltage. If the forward bias current between the cathode and gate is further increased, the forward breakover voltage will be further decreased. This is shown in Figure 5.
The breakover voltage is high when there is no forward bias current (Igt0) between the gate and the cathode. When a small forward bias current (Igt1) is flowing, the SCR is switched to a high conduction state at a lower breakover voltage. At (Igt2), the forward bias current between the cathode and the gate is sufficient to produce a high state of conduction when the anode is only a few volts positive.
From the preceding discussion, it can be seen that a voltage at the gate can control the firing of the SCR.After the SCR is fired, or turned on, the gate loses control over the SCR. This means that the gate can control the SCR until it is switched on, but after the SCR is in a high state of conduction, the gate voltage has no affect on the SCRs operation. In fact, the gate voltage can be removed after the SCR is conducting. Also, it is only necessary for the gate voltage to be a pulse of short duration to drive the SCR into conduction.
After the SCR is in its "on" state, it is switched back to its "off" state by decreasing the anode current below its holding current level.
The SCR shown in Figure 6 has a forward breakover voltage in the absence of a gate signal that is much higher than the supply voltage. Consequently, when the switch is open, there will only be a small flow of anode current because the SCR is in its forward blocking state.
Figure 6: SCR Circuit Arrangement
The SCR normally is operated with a positive potential at the anode with reference to the cathode. The SCR will not conduct a significant flow of current unless the forward breakover voltage is exceeded. Normally, SCRs are chosen to have a forward breakover voltage in the absence of a gate signal that is much higher than any of the circuit voltages.
R1 and R2 form a voltage divider across VCC. R1 is variable. When the switch is closed, a voltage will be developed between the gate and the cathode (Vgt). As a result of this voltage, there will be a flow of current (Igt) in the gate-cathode circuit. This reduces the value of the forward breakover voltage. If Vgt and Igt are sufficient, the forward breakover voltage will be lowered to a value that is less than VCC; consequently, the SCR will be switched into a high state of conduction and the current through R3 will increase.
After the SCR is triggered, the gate voltage has no effect on the operation of the SCR. It is only necessary for Vgt and Igt to be present for a period of time that will allow the SCR to switch from its "off" state to its "on" state.
The SCR is primarily used to control the application of DC or AC power to various types of loads. It can be used as a switch to open or close a circuit, or it can be used to vary the amount of power applied to a load. A very low current gate signal can control a very large load current, as in Figure 7.
Figure 7: SCR DC Switching CircuitAn SCR may also be used to control the application of AC power to a load. When used in AC circuits, the device is capable of operating on only one alternation of each AC input cycle. A simple AC switch circuit is shown in Figure 8. The SCR can conduct only on those alternations that make its anode positive with respect to its cathode. The SCR gate circuit acts as a switch (S) The output load acts as a resister (R). Switch S must also be closed so that gate current will flow through the SCR and allow it to conduct. Therefore, by gating switch S, the SCR is allowed to conduct on one alternation of each input cycle and apply this portion of the AC voltage to load resistor RL. When switch S is gated off, the SCR will turn off within one-half cycle of the AC signal. In other words, when no gate current can flow through the SCR, the device will turn off as soon as the AC input voltage drops to zero and starts increasing in the direction that causes the SCRs anode to be negative with respect to its cathode. The SCR will remain off until the switch is closed again.
Figure 8: SCR AC Half-Wave Phase Control Switching CircuitThe circuits previously discussed were simply used to apply or remove electrical power and take the place of a mechanical switch. However, when compared to mechanical switches or relays, these SCR circuits have many advantages. They do not wear out like mechanical devices, and they do not have contacts that can bounce or stick and cause intermittent operation. The SCR circuits are much more reliable than mechanical devices in applications where large amounts of power must be controlled. SCR circuits may, in turn, be controlled mechanically or electrically. In either case, it is only necessary to control the SCRs very small gate current. If this is done mechanically, a relatively inexpensive switch that has low current and voltage ratings can be used.
SCRs may also be used to vary the amount of power applied to a load instead of just simply switching the power on or off. In fact, they are widely used in power control applications where the source of power is 60 Hz AC. One of the most basic AC power control circuits that uses an SCR is shown in Figure 9. This circuit is commonly referred to as a full-wave phase control circuit. It uses two SCRs and it is capable of controlling the AC power applied to load resistor RL.
Figure 9: SCR Full-Wave Phase Control CircuitFigure 10 shows the SCR voltage output, and Figure 11 shows the SCR current output signal
Figure 10: SCR Rectifier Voltage Output Waveform
Figure 11: SCR Rectifier Current Output WaveformAs shown, the full-wave phase control circuit is capable of controlling the amount of power applied to the load. In this circuit, the power applied to the load can be varied from zero to approximately 90% of the input AC power, based on the gate control signal applied to the SCRs.
A triac is a three-terminal device similar in construction and operation to the SCR. Figure 12 shows the schematic symbol for a triac.
Figure 12: Triac ConstructionBoth the SCR and the triac have a gate lead. However, in the triac the lead on the same side as the gate is "main terminal 1" and the lead opposite the gate is "main terminal 2." This method of lead labeling is necessary because the triac is essentially two SCRs back-to-back, with a common gate and common terminals. Each terminal is, in effect, the anode of one SCR and the cathode of another and either terminal can receive an input. In fact, connecting two SCRs, as shown in Figure 13, can duplicate the function of a triac. The result is a three-terminal device identical to the triac. The common anode-cathode connections form main terminals 1 and 2, and the common gate forms terminal 3. The gate basically is capable of directly triggering either equivalent SCR into conduction. Notice that both of the SCR gates are tied together to show the equivalent relationship.
Figure 13: Triac Equivalent CircuitUnlike an SCR, which can control currents flowing in only one direction, the triac can control currents flowing in either direction. Therefore, the triac is widely used to control the application of AC power to various types of loads or circuits. The conditions required to turn a triac on or off in either direction are similar to the conditions required to control an SCR. Both devices can be triggered to the "on" state by a gate current, and they can be turned off by reducing their operating currents below their respective holding values. In the case of an SCR though, current must flow in the forward direction from cathode to anode. However, the triac is designed to conduct both forward and reverse currents through its main terminals.
Figure 14: Diac Schematic Symbol and Equivalent CircuitThe diac remains in an "off" state, conducting only a small leakage current, until the applied voltage in either direction is high enough to cause its respective reverse-biased junction to break down. When this happens, the device turns on and current suddenly rises to a value that is essentially limited only by the resistance in series with the device. The diac, therefore, functions as a bi-directional switch that will turn on whenever its breakdown voltage is exceeded in either direction.
The diac is used as a triggering device because the triac is not equally sensitive to gate currents flowing in opposite directions. The triggering device helps to compensate for the triacs non-symmetrical, or non-uniform, triggering characteristics. The voltage required to turn on the diac is identical in either direction, and the device is designed to be as insensitive to temperature changes as possible. The diac works in conjunction with resistor Rεand capacitor Cεto produce consistently accurate gate current pulses that are high enough to turn on the triac at the proper time in either direction. These gate current pulses can have durations as short as several microseconds and still trigger the triac.
The peak value and duration of the current pulses applied to the gate are determined by the value of Cε, the resistance of the diac, and the resistance between the triacs gate and MTεterminals.
Figure 15: UJT SymbolThe N-type bar is lightly doped; therefore, the resistance between the base 1 and base 2 leads is quite high. The area in which the P-type pellet and N-type bar meet to form a PN junction has characteristics similar to those of a PN-junction diode. Therefore, we can represent the UJT with an equivalent circuit. This equivalent circuit consists of two resistors and a diode that has its cathode end connected between the resistors. The operation of the UJT is much easier to understand when this equivalent circuit is used in place of the UJTs basic structure.
The schematic symbol that is commonly used to represent the UJT is also shown in Figure 15. The emitter in the schematic symbol is identified by an arrow pointing between the bases at an angle, with the arrow pointing toward base 1. The arrow on the emitter lead points inward to show that the UJT has a P-type emitter.
Figure 16: UJT BiasingThe operation of an ordinary UJT is more apparent when its equivalent circuit is analyzed (Figure 17). The resistance RBεis shown as a variable resistor since its value will vary with the emitter current (IE). RB1is a fixed value resistor. The value of resistance between Bεand B1is called the interbase resistance.
Figure 17: UJT Equivalent CircuitBefore VE is applied, there is a small flow of current between B2 and B1, which is determined by the magnitude of VBB and the value of the interbase resistance. The interbase resistance is relatively large, so the current is small. Voltages will be developed across RB2 and RB1 because of the current flow. The cathode of the diode is positive with reference to B2. As a result, there will not be a flow of current between the emitter and B2 until the emitter voltage is 0.7 V more positive than the voltage across RB2.
When the emitter voltage exceeds the voltage across RBεby 0.7 V, the diode is forward biased and current will flow between the emitter and base 1. Holes from the P-type emitter region flow toward the N-type base, or Bε, which produces an increase in the electron flow into Bε. As a result, the density of current carriers in the base 1 region increases and causes the effective opposition of RBεto decrease. When the resistance of RBεdecreases, the voltage across it decreases; therefore, the forward bias between the emitter and Bεis further increased. This produces more emitter-Bεcurrent and RBεis further reduced. This regenerative feedback effect continues until RBεreaches some minimum value.
Emitter voltage is equal to the drop across RBεplus the drop across the PN junction, so the emitter voltage also decreases. This is called the UJTs negative resistance region because an increase in Bεto B1current is produced by an apparent decrease in voltage at the emitter.
The forward bias potential at the emitter quickly reduces the opposition of RBε. RBεis in series with RBε; consequently, when the opposition of RBεdecreases, the current from Bεto B1will increase. Once a sufficient amount of forward bias is applied to the emitter, the UJT is switched from a high-resistance "off" state to a low-resistance "on" state.
Figure 18: UJT Relaxation OscillatorWhen power is applied, capacitor C1 charges through resistor R1. When the voltage across C1 reaches the UJTs peak voltage (VP) value, the UJT turns on. This allows C1 to discharge through the UJT and resistor R2. The voltage across C1 quickly decreases to the UJTs valley voltage (VV) value and causes the UJT to stop conducting or turn off. As soon as the UJT turns off, capacitor C1 starts charging again and continues until VPis again reached. This action continues, with the voltage across C1 rising slowly to VPand decreasing rapidly to VV.
The voltage appearing between the UJTs B1 and B2 terminals fluctuates, as shown in Figure 19. Notice that this voltage follows a sawtooth type of pattern and, after initial turn-on, varies only between VVand VP.
Figure 19: UJT Relaxation Oscillator Waveforms
Each time capacitor C1 discharges, current is momentarily forced through R2. These momentary pulses of current cause the voltage across R2. Notice that the pulses are very narrow, and a pulse occurs each time C1 discharges. Also, notice that the voltage never drops completely to zero. A small voltage will always be dropped across R3, because a small current flows through the UJT from B1 to B2 even when the device is in the "off" state.
Basically there are two types of field effect transistors. One type is known as a junction field effect transistor, commonly referred to as a JFET. The second type is known as an insulated gate field effect transistor (IGFET), although it is frequently referred to as a metal-oxide semiconductor field effect transistor, or MOSFET.
The structure created by this process is shown in Figure 20. The region that is embedded in the substrate material is U-shaped so that it is flush with the upper surface of the substrate at only two points. The embedded region actually forms a channel of oppositely doped semi-conductor material through the substrate. When this channel is made from an N-type material and embedded in a P-type substrate, the entire structure is known as an N-channel JFET. However, when a P-type channel is implanted in an N-type substrate, the device becomes a P-channel JFET.
Figure 20: FET Junction Construction
Making three electrical connections to the device, as shown in Figure 20, completes the construction of a JFET. One lead is attached to the substrate and is referred to as the gate. Leads are then attached to each end of the channel and are referred to as the source and the drain.
Like a conventional bipolar transistor, a JFET requires two external bias voltages for proper operation. One voltage source is normally connected between the source and drain leads so that a current is forced to flow through the channel within the device. The second voltage is applied between the gate and the source and is used to control the amount of current flowing through the channel.
Figure 21 shows a cross-sectional view of an N-channel JFET and its required operating voltages. Notice that an external voltage source represented by the symbol VDSis connected between the drain (D) and the source (S) leads. The voltage is connected so that the source is made negative with respect to the drain. This voltage causes a current to flow through the N-type channel because of the majority carriers (free electrons) within the N-type material. This source-to-drain current is commonly referred to as the FET drain current and is represented by the symbol ID. The channel simply appears as a resistance to the supply voltage VDS.
Figure 21: Cross-Sectional View of an N-Channel JFETNotice that a voltage is also applied between the gate (G) and the source (S) of the FET. This gate-to-source voltage, designated as VGS, causes the P-type gate to be negative with respect to the N-type source. Since the source is effectively just one end of the N-type channel, VGSeffectively reverse-biases the PN junction formed by the P-type gate and the N-type channel. This reverse bias voltage causes a depletion region to form within the vicinity of the PN junction. This depletion region extends around the wall of the N-type channel since all sides of the channel are in contact with the P-type substrate. The depletion region will be somewhat wider at the drain end of the channel than at the source end. This is because VDSeffectively adds to VGSso that the voltage across the drain end of the PN junction is higher than the voltage across the source end of the junction.
The size of the depletion region is controlled by voltage VGS. When VGSincreases, the depletion region increases in size. When VGSdecreases, the depletion region decreases in size. Furthermore, when the depletion region increases in size, the N-type channel is effectively reduced in size. Fewer free electrons are available, and less current will be able to flow through the channel. The opposite is true when the depletion region decreases in size. This means that VGSmay be used to effectively control the drain current (ID) flowing through the channel. An increase in VGSresults in a decrease in IDand vice-versa; therefore, VGSeffectively controls the resistance of the channel. Also, VGSreverse-biases the PN junction formed by the gate and the channel; therefore, only an extremely small leakage current flows from the gate to the source.
In normal operation, the voltage applied between the gate and the source serves as an input voltage to control the device. The drain current represents the output current that can be made to flow through a load. This action is considerably different from the action that takes place in a bipolar transistor. In the transistor, an input current - not a voltage - is used to control an output current. Also, since the gate-to-source junction of the FET is reverse-biased by VGS, the FET has an extremely high input resistance. This is just the opposite of a bipolar transistor, which has a forward-biased emitter-to-base junction and, therefore, a relatively low input resistance. The gate-to-source voltage must never be reversed so that the PN junction formed by the gate and the channel becomes forward-biased. This would result in a relatively large current through the junction, causing the input resistance of the device to drop to a low value.
As previously mentioned, when VGSis increased, the depletion region within the FET increases in size and allows less drain current to flow. If VGSis increased to a sufficiently high value, the depletion region is increased in size until the entire channel is depleted of majority carriers. This causes IDto decrease to an extremely small value. For all practical purposes, it is reduced to zero. The gate-to-source voltage required to reduce IDto zero, regardless of the value of VDS, is referred to as the gate-to-source cutoff voltage.
To this point, we have examined only the N-channel junction FET. A P-channel FET operates in the same manner as the N-channel device, and it has the same basic characteristics. The primary difference is the manner in which the drain current flows through the channel. Also, the P-channel FET has a gate or substrate that is formed from N-type material. This, of course, is opposite to the conditions that exist within an N-channel FET. This means that the polarities of the bias voltages VGSand VDSare exactly opposite for the N-channel and P-channel devices.
An N-channel JFET and P-channel JFET are shown in Figure 22 as they would appear in a circuit diagram or schematic. The required bias voltages for each device are also shown. Notice that the symbols used for each device are almost identical. The only difference is the direction of the arrow on the gate (G) lead.
Figure 22: N-Channel and P-Channel Junction FET BiasingJust as it does in transistor symbols, the arrow in a JFET symbol always points toward the N-type material. Thus, the symbol of the N-channel JFET shows the arrow pointing toward the channel, whereas the P-channel symbol shows the arrow pointing away from the channel, toward the gate.
Also notice that the polarities of the bias voltages are exactly opposite. The N-channel FET must be biased so that its drain (D) is positive with respect to its source (S), and its gate (G) must be negative with respect to the source.
The P-channel FET must be biased so that its drain is negative with respect to its source, and its gate must be positive with respect to the source. The drain current (ID) will therefore flow in a direction opposite to that in an N-channel FET.
Unlike the JFET, which operates in only the reverse bias, or depletion, mode, the MOSFET is designed to operate as either a depletion-mode device or an enhancement-mode device. The depletion-mode MOSFET has a heavily doped channel and uses reverse bias on the gate to cause a depletion of current carriers in the channel. The enhancement-mode MOSFET has a lightly doped channel and uses forward bias to enhance the current carriers in the channel. In addition to the two basic modes of operation, the MOSFET, like the JFET, is of either the P-channel type or the N-channel type. Each type has four elements: the gate, source, drain, and substrate. The schematic symbols for the four basic variations of the MOSFET are shown in Figure 23.
Figure 23: MOSFET Configurations
Figure 24: Depletion-Mode MOSFET StructureThere is no electrical connection between the gate and the rest of the device. This construction method results in the extremely high input impedance of the MOSFET. The insulated gate controls the conductivity of the device, depleting the N-type channel of majority carriers (electrons) when a suitable bias voltage is applied even though a semiconductor junction does not exist between the gate and the channel.
The operation of an N-channel depletion-mode MOSFET is shown in Figure 25. Its source and drain leads are biased in the same manner as the leads of an N-channel junction FET; the drain is always made positive with respect to the source. The majority carriers (electrons) within the N-type channel therefore allow current to flow through the channel from source to drain. A gate-to-source bias voltage controls this source-to-drain current, normally called drain current. When the gate-to-source voltage is equal to zero, a substantial drain current will flow through the device because a large number of majority carriers are present in the channel. If the gate is made negative with respect to the source, the channel becomes depleted of its majority carriers and drain current decreases. If this negative gate voltage is increased to a sufficiently high value, the drain current will drop to zero.
Figure 25: N-Channel Depletion-Mode MOSFET OperationThe MOSFET can also handle a positive gate voltage, because the silicon dioxide insulating layer prevents any current from flowing through the gate lead. The FETs input resistance, therefore, remains at a high value. When a positive voltage is applied to the gate, more majority carriers (electrons) are drawn into the channel, thus enhancing the conductivity of the channel. This is exactly opposite to the action that takes place when the gate receives a negative voltage. A positive gate voltage can, therefore, be used to increase the FETs drain current, while a negative gate voltage will decrease the drain current.
Since a negative gate voltage is required to deplete the N-channel and reduce its drain current, this FET is called a depletion mode device. Like the JFET, this device conducts a substantial amount of drain current when its gate voltage is equal to zero. All depletion-mode devices, either junction or insulated gate types, are said to be normally conducting, or normally on, when their gate voltages are zero.
The schematic representation of a properly biased N-channel depletion-mode MOSFET is shown in Figure 26. Notice that the gate (G) lead is separated from the source (S) and drain (D) leads. Also, the arrow on the substrate lead designated as SS, or B, points inward to represent an N-channel device.
Figure 26: Properly Biased N-Channel Depletion-Mode MOSFETA depletion-mode MOSFET may also be constructed using a P-type channel that is implanted within an N-type substrate. Such devices generally are referred to as P-channel depletion-mode MOSFETs. These P-channel devices operate in basically the same manner as the N-channel devices; however, the majority carriers within the P-type channel are holes instead of electrons. Furthermore, the drain lead of the P-channel device must be made negative with respect to its source lead so that its drain-to-source voltage is exactly opposite to the VDSapplied to the N-channel device. This means that the drain current (ID) must flow in the opposite direction. The gate may also be made negative or positive with respect to the source, as with the N-channel device.
Figure 27: Enhancement-Mode MOSFET StructureThe operation of an N-channel enhancement-mode MOSFET is shown in Figure 28. The device must be biased so that its drain is made positive with respect to its source. With only a drain-to-source voltage (VDS) applied, the FET does not conduct a drain current (ID). This is because no conducting channel exists between the source and drain regions. This situation can be changed with the application of a suitable gate voltage. When the gate is made positive with respect to the source, electrons are drawn toward the gate. These electrons accumulate under the gate, where they create an N-type channel that allows current to flow from source to drain. When this positive gate voltage increases, the size of the channel also increases, thus allowing even more drain current to flow.
Figure 28: N -Channel Enhancement-Mode MOSFET OperationThe action just described is similar to the action that takes place in a charging capacitor. The metallic gate and the substrate act like the upper and lower plates of a capacitor, and the insulating layer acts like the dielectric. The positive gate voltage simply causes the capacitor to charge, and a negative charge builds up on the substrate side of the capacitor. The positive gate voltage effectively induces an N-type channel between the source and drain regions, which sustains a drain current. An increase in gate voltage tends to enhance the drain current; therefore, this FET is termed an enhancement-mode device.
The gate of the N-channel enhancement-mode MOSFET can also be made negative with respect to its source. However, a negative gate voltage will not affect the operation of the FET since it is a normally-off (non-conducting) device. The FETs drain current is statically equal to zero and therefore cannot be further reduced by application of a negative gate voltage.
Figure 29 is the schematic representation of a properly biased N-channel enhancement-mode MOSFET. Notice that this symbol is similar to the symbol for the N-channel depletion-mode MOSFET. The only difference is the use of an interrupted line instead of a solid line to interconnect the source, drain, and substrate regions. The solid line is used to identify the normally-on condition of the depletion-mode device, while the interrupted line is used to identify the normally-off condition of the enhancement-mode device. In each symbol, the arrow points inward to indicate that each device has an N-type channel.
Figure 29: Properly Biased N-Channel Enhancement-Mode MOSFETAn enhancement-mode MOSFET may also be constructed using P-type source and drain regions that are implanted in an N-type substrate. This type of FET must be operated with a negative gate voltage so that holes instead of electrons are attracted toward the gate to form a P-type channel. Such a device is referred to as a P-channel enhancement-mode MOSFET. The P-channel device functions basically the same as the N-channel device even though holes instead of electrons are used to support drain current through the device. The P-channel device requires bias voltages (VGSand VDS) that are opposite to those shown in Figure 29.
Field effect transistors are placed into three basic circuit configurations, just like ordinary transistors. These configurations are called the common source, common drain, and common gate and are shown in Figure 30. In terms of ordinary transistors, they correspond to the common emitter, common collector, and common base configurations, respectively.
Figure 30: Field Effect Transistor Circuits
Table 1 presents the important characteristics of field effect transistors in the various circuit configurations. These circuit connections are valid for both JFETs and MOSFETs.
Figure 31 shows a basic common source amplifier circuit containing an N-channel JFET. The characteristics of this circuit include high input impedance and high voltage gain. The functions of the circuit components in this figure are very similar to those in a transistor common emitter amplifier circuit. CÃƒÆ’Ã…Â½Ãƒâ€šÃ‚Âµand C1are the input and output coupling capacitors. RÃƒÆ’Ã…Â½Ãƒâ€šÃ‚Âµis the gate return resistor and functions much like the base return resistor in a transistor circuit. It prevents unwanted charge buildup on the gate by providing a discharge path for CÃƒÆ’Ã…Â½Ãƒâ€šÃ‚Âµ. R1and C1provide source self-bias for the JFET, which operates like emitter self-bias. R is the drain load resistor, which acts like the collector load resistor.
Figure 31: Common Source Amplifier
The phase shift of 180? between the input and output signals is the same as seen in common emitter transistor circuits. The reason for the phase shift can be seen easily by observing the operation of the N-channel JFET. On the positive alternation of the input signal, the amount of reverse bias on the P-type gate material is reduced, thus increasing the effective cross-sectional area of the channel and decreasing source-to-drain resistance. When resistance decreases, current flow through the JFET increases. This increase causes the voltage drop across R to increase, which in turn causes the drain voltage to decrease. On the negative alternation of the cycle, the amount of reverse bias on the gate of the JFET is increased and the action of the circuit is reversed. The result is an output signal that is an amplified 180? out-of-phase version of the input signal.